Current art semiconductor wafer processing technologies, including materials such as gallium arsenide (GaAs) and indium phosphide (InP), require various methods, such as wet etching, for improving vertical sidewall structures. Historically, wet etching has involved immersion techniques and spray techniques. In wet etching by immersion, a wafer is immersed in a tank of etchant for a period of time, rinsed, and then spin-dried. In wet etching by spraying, a wafer is sprayed with an etchant, rinsed, and then dried. These wet etching techniques are only effective for semiconductor devices having feature sizes of greater than three microns. Unfortunately, these wet etching techniques tend to result in inchoate etching, over-etching, or undercutting problems. In addition, wet etching results in isotropic sloped sidewalls, require rinsing and drying steps, involves hazardous wet chemicals, and presents potential contamination.1 1Microchip Fabrication: A Practical Guide to Semiconductor Processing, 4th Ed., Peter Van Zant, pp. 256–263, Plasma Etch Gas Chart, FIG. 9.25 (McGraw-Hill, 2000).
Other related art wet etching processing technologies have conventionally used an etchant, such as difluoro-dichloromethane (CCl2F2) or Freon 12®, for processing GaAs with a trend toward using a combination of silicon tetrachloride and sulphur hexaflouride (SiCl4/SF6), a combination of silicon tetrachloride and nitrogen trifluoride (SiCl4/NF3), and a combination of silicon tetrachloride and carbon tetrafluoride (SiCl4/CF4) as the etchant. While no conventional etchant has been used for wet etching InP, a trend exists toward using a combination of methane and hydrogen (CH4/H2) or only hydrogen iodide, i.e., hydroidoic acid (HI) as the etchant.2 2Id., at 266.
However, these related art reaction gas combinations have been found to result in poor device quality. While etching any one layer of a multi-layer semiconductor structure in a related art device, these related art techniques also tend to have the effect of either prematurely self-terminating the etching of the multilayer semiconductor structure or over-etching the multilayer semiconductor structure, thereby inflicting damage on the surface of the semiconductor wafer, e.g., undercutting (mathematically positive slope profile) and metallization punch-through occurring on an upper surface of a semiconductor structure such as on an upper surface of a via.
Particularly, prior art FIG. 1 is a cross-sectional view of a plasma-etched semiconductor structure 10 having a mask 11 thereon deposited, wherein the reaction gas mixture comprises a combination of chlorine (Cl2) and nitrogen (N2) at a volume ratio of 3Cl2:1N2, and wherein a conventional reaction chamber is used. The reaction chamber parameters typically used in this prior art are: a temperature value of 100° C.; a negative bias power value of 30 W; an inductively coupled power value of 500 W; and a pressure value of 5 mTorr. Experimental results have shown that the structure 10, which is formed on a semiconductor wafer 100 of a semiconductor device 1000, has sustained substantial sidewall 12 damage, i.e., an over-etched mask (excessive loss of SixNy), a roughly tapered or sloped sidewall (mathematically negative slope profile), and wafer surface 13 damage, i.e., roughness, in accordance with the prior art.
Therefore, a long-felt need remains for a process that will selectively etch multiple layers of semiconductor material without prematurely self-terminating the etching nor over-etching the multilayer semiconductor structure, thereby eliminating damage on the surface of the semiconductor wafer, and thereby preventing damage to semiconductor structures such as emitters.